system verilog - Casting to a fixed width signed number -

i reading register field uvm ral model. field 14 bit signed number, ral has no sense of sign need grab relevant bits , cast them signed number

uvm_reg_data_t reg_value; int destination;  reg_value = reg_field.get(); assign destination = signed'(14'(reg_value));

is there way 1 cast? know define type , use that, wondering if there syntax work:

assign destination = (14's)'(reg_value);

there no such syntax in single cast without typedef. do

assign destination = signed'(reg_value[13:0]);

but think creating typedef field type best show intent.

Today